1. Field of the Invention
The present invention relates to a packaging technique of semiconductor integrated circuit devices and, more particularly, to mounting devices for semiconductor integrated circuit chips capable of high speed logic performance.
2. Description of the Related Art
With the increasing needs for high speed logic performance of digital systems, a great deal of attention is paid to gallium arsenide (to be referred to as GaAs hereinafter). Recently, integrated circuit devices capable of high speed logic performance at a switching speed of about 100 picoseconds have been developed by integrating GaAs Schottky gate field effect transistors (metal-semiconductor field effect transistors or "MESFETs". The packaging technique of such high-speed devices, however, is still under development.
If chips of high-speed devices are mounted on packages of conventional structures, high performance of the devices themselves cannot be fully obtained. This is because high-speed signal transmission efficiency is degraded in the wiring (normally, bonding wiring) between the device chips and the packages. Degradation in signal transmission characteristic in IC packages results not only from degradation in impedance-matching in connecting terminals but also from the fact that, in high-speed transmission of logical signals, bonding wires themselves adversely behave as an "open stub", which degrades uniformity of signal processing characteristic of a device.